The present invention relates to semiconductor devices and a method for fabricating the same, and more specifically relates to a semiconductor device having a trench capacitor and a method capable of fabricating the semiconductor device easily.
As known well, in the prior art, dynamic random access memory (DRAM) has realized improvement of the integration degree being four times in the three years, and the mass production of the DRAM of 4 mega bits has been already carried out and the development directed to the mass production of the DRAM of 16 mega bits is being advanced.
Such high integration of the DRAM has been achieved by reducing the element size, but due to decrease of the charge storage capacity attendant on the miniaturization, disadvantages such as decrease of signal-to-noise ratio or change "1" to "0" due to .alpha.-particle irradiation, are actualized, and it becomes difficult to maintain the reliability.
Therefore in the present, as a memory cell capable of increasing the charge storage capacitor, the mainstream of cells of 4 mega bits and so forth is in a stacked cell where a part of the charge storage capacitor is stacked on a switching transistor or a field isolation oxide, or in a trench type cell where a deep trench is formed on a substrate and a charge storage capacitor is formed to a side wall of the trench.
Further, the trial manufacture of the DRAM of 16 mega bits or 64 mega bits is being tried, using a three-dimensional cell structure where such cells are arranged in the three dimensions up and down and the self-align process. However, if the area of the memory cell is made small along the trend up to now, the cell area becomes about 0.5 square microns in the DRAM of 256 mega bits and becomes about 0.15 square microns in the DRAM of 1 giga bit. Consequently, even if the above-mentioned three-dimensional capacitor cell is used, sufficient storage capacitor cannot be obtained and it is difficult to reduce the cell area.
A memory cell is constituted by minimum unit of a capacitor for storing charge, bit lines for supplying charge to the capacitor, and word lines for controlling the flow of charge. Therefore, a very small memory cell can be fabricated in comparison with other semiconductor memory devices.
FIG. 5 is a sectional view showing a semiconductor memory device having a trench type capacitor in the prior art. A trench capacitor cell of this structure is disclosed in Japanese patent application laid-open No. 136559/1988. Electrodes to constitute a charge storage capacitor are composed of a storage capacitor electrode contacting with a diffusion layer of a switching transistor and an opposite electrode opposed to the storage capacitor electrode. This structure is characterized in that a plate 16 being an opposite electrode is formed within a substrate self-alignedly. That is, a bottom portion of a silicon dioxide film 8 to cover the inner wall of the trench is removed selectively, and a polycrystalline silicon film to be used as a plate is formed within the trench and subjected to patterning into a desired form, and then impurity being different from the substrate in the conductivity type is diffused through the polycrystalline silicon. Since trenches are closely aggregated within the substrate, the impurity diffused layers are connected to each other by the thermal process in usual temperature of about 900.degree. C. and a meshed plate is formed.
In order to realize this structure, however, complicated processes are required such that at first, a silicon dioxide film on the bottom of the trench is removed, and a polycrystalline silicon 9 within the trench is dug down as shown in FIG. 5, and only a part of the side wall of the silicon dioxide film 8 is removed, in order to connect a diffusion layer 5 of a switching transistor with a polycrystalline silicon 11 filling the inside of the trench. Also since a junction is produced within the substrate, leak current may occur between the plate and the substrate. Thus the semiconductor memory device of trench type as shown in FIG. 5 has a structure which is not always suitable for miniaturization, because its fabricating method is complicated.
In FIG. 5, numeral 1 designates a semiconductor substrate, numeral 2 designates a gate silicon dioxide film of a switching transistor, numeral 3 designates a gate electrode of a switching transistor, numeral 4 designates a silicon dioxide film, numeral 5 designates a diffusion layer, numeral 6 designates a side wall silicon dioxide film of a switching transistor, numeral 7 designates a trench, numeral 8 designates a trench side wall silicon dioxide film, numeral 9 designates a plate electrode within a trench, numeral 10 designates a capacitor insulation film, numeral 11 designates a capacitor storage electrode contacting with a diffusion layer of a switching transistor, numeral 13 designates an interlayer insulation film, numeral 14 designates a bit line, numeral 18 designates a polycrystalline silicon to connect a diffusion layer with a polycrystalline silicon within a trench on a surface of a substrate, and numeral 19 designates a polycrystalline silicon film through which a bit line and a diffusion layer are connected, respectively.
The most serious problem in the structure of the above-mentioned memory cell is caused by that the polycrystalline silicon 11 filling the inside of the trench and the diffusion layer of the switching transistor must be connected electrically. That is, a part of upper side of the silicon dioxide film 8 to cover the side wall of the trench must be removed. In this case, since the upper side of the trench silicon dioxide film 8 contacting with a field isolation oxide 15 must be protected, a mask pattern must be used. As a result, alignment tolerance is necessary between the gate electrode 3 of the switching transistor and the trench 7. Also impurity is diffused from the polycrystalline silicon 11 into the substrate 1 through the part where the trench silicon dioxide film 8 is removed. In order that the impurity does not adversely affect the characteristics of the switching transistor, the distance between the gate electrode and the trench cannot be made so small and the tolerance must be considered.
Due to such problems, it is difficult that the trench cell shown in FIG. 5 is further miniaturized.
Not only the trench cell but also that of other type, although the cell can be constituted by the minimum area in structure in the dynamic random access memory, reduction of the area of the memory cell is limited by such alignment tolerance, and the connecting part between the bit line and the diffusion layer, and the word line arrangement on the field isolation oxide 15 in the cell of so-called folded bit-line structure as shown in FIG. 5.